Abstract

Resistive switches in crossbar arrays introduce one potential option to push past the limits of CMOS process scaling, with advantages including low switching thresholds (<3 V), high integrability with CMOS, and fast switching speeds (<10 ns). These typically employ a 1T1R scheme for each cell, where the transistor is deployed for selection and sneak path mitigation. However, when conductive filaments are formed in metal-oxide resistive switches, it is often the case that analog states are not thermodynamically favorable, and will spontaneously set or reset to a more stable state. This causes stochastic switching, variability, and non-reproducibility, in a manner which cannot be harnessed in stochastic gradient descent. Equally important is the memory leakage problem that is introduced. In this work, we present a generalized neuron model of resistive switching in the development of a phase plane characterization, and verify its operation by comparing it to our own in-house fabricated thin-film titanium-oxide memristor array. We show an alternative design methodology that draws inspiration from the leaky-integrate-and-fire neuron model. The advantages exhibited by such a methodology are to provide more biologically accurate neuronal model and to enable large scale simulations, demonstrated by the 30% improvement in speed over similar device models.

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