A leakage-suppression technique for phase-locked systems in 65nm CMOS

Abstract

In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current results in a high stand-by power consumption. For analog circuits, it degrades the accuracy and performance. PLLs are widely used in various wireline and wireless communication systems. For a phase/frequency detector (PFD) and a divider in a PLL, the leakage current increases the in-band phase noise and jitter. For a VCO, the leakage current alters the common-mode voltage, and as a result the VCO may not operate at a low frequency [3]. For a charge pump (CP) and a loop filter, the leakage current induces a steady phase error and jitter. It is because the leakage current charges or discharges the loop filter while the CP is off. Since a PLL usually needs a large capacitor in its loop filter, the MOS capacitor is often used to save the area. However, the large MOS capacitor suffers from the large leakage current in a nanoscale CMOS process. An analog method to suppress the leakage current for the MOS capacitor is reported in [4]. This method works well under a low leakage current. However, once the leakage current is large enough, e.g., several 100µA, an operational amplifier with a high current-drive capability is required.