A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology

Abstract

Level Shifters (LSs) are critical components in Multi Supply Voltage Domain (MSVD) designs especially when signals need to be converted from the sub-threshold to the above-threshold domains. The design of a LS can greatly benefit from the adoption of recent advanced technologies, such as the Ultra-Thin Box and Body Fully-Depleted Silicon On Insulator (UTBB FDSOI) technology that has emerged as an attractive alternative to the traditional bulk CMOS. The UTBB FDSOI technology provides a group of device and architectural techniques suitable to realize a wide threshold voltage (Vth) tuning, such as flip well, poly biasing and body biasing. In this paper, the synergistic adoption of such knobs is investigated in the design of low-power high-performance LSs. A new single-well layout strategy is proposed to smartly realize an aggressive forward body biasing in the converting stage of the LS. In conjunction with poly biasing, the proposed strategy reduces the energy per cycle and the leakage of up to 35.3% and 70.4%, respectively. Moreover, the minimum input voltage that the LS can correctly up-convert is also improved.