A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Abstract

Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.