Abstract
A 64-bit parallel correlator is described using a large-scale integrated single-chip bipolar transistor construction. The circuit operates at 20 MHz and has an analog correlation output. The LSI structure uses the triple diffusion process, which produces both n-p-n and p-n-p transistors. Resistors are also diffused. A combination of soft saturated register circuits and nonsaturating gating circuits produce a 25-pJ gate performance with device f/SUB t/ in the range 50-150 MHz. The logic form used is emitter-follower logic. This 5000 device, 220- by 230-mil chip, is a highly producible LSI function.
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