A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs

Chongyan Gu,Weiqiang Liu,Chip Hong Chang,Máire O'Neill,Neil Hanley,Jack Miskelly

doi:10.1145/3338508.3359570

Abstract

Many field programmable gate array (FPGA)-based security primitives have been developed, e.g., physical unclonable functions (PUFs) and true random number generator (TRNG). To accurately evaluate the performance of a PUF or other security designs, data from a large number of devices are required. A slice is the smallest reconfigurable logic block in an FPGA. The maximum or minimum entropy, exploitable from each slice of an FPGA, is an important factor for the design of a single-bit disorder-based security primitive. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (PicoPUF) cells that can each be fully fitted into a single slice are evaluated. 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time two different single slice based security entities have been investigated and compared on 28nm Xilinx FPGA. Experimental results, including uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy, based on 4 different floorplan locations are presented. The experimental results demonstrate that the lower the correlation between devices, the higher the min-entropy and uniqueness for both designs on the FPGAs. While the implementation location of both designs on the FPGA affects their performances, the overall min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. All other metrics, including uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. The raw data for the PicoPUF design is made publicly available to enable the research community to use them for benchmarking and/or validation.

Highlights

Due to its reconfigurability and fast design turnaround time, field programmable gate array (FPGA) has become an attractive target platform for developing hardware security primitives such as physical unclonable functions (PUFs) and true random number generator (TRNG)
In this work we presented a large scale analysis of two single-slice based bit cells on 217 Xilinx Artix-7 XC7A35T FPGAs
The experimental results show that the overall minentropy, correlation and uniqueness of PicoPUF are slightly higher than that of ring oscillator (RO), while the other metrics, including uniformity, bit-aliasing and reliability are slightly lower than that of RO

Summary

Introduction

Due to its reconfigurability and fast design turnaround time, FPGA has become an attractive target platform for developing hardware security primitives such as PUF and TRNG. Since the physical disorder properties introduced by process variations among different nano-scale devices on the same monolithically integrated chip is outside the control of the manufacturer, PUFs are inherently difficult to clone. A PUF circuit has a number of desirable features for security applications, such as the ability to provide lowcost unforgeable identity of an integrated circuit (IC) or to return a device-specific response to an input challenge for chip authentication. These unique device-intrinsic properties can be utilized in a number of different use cases, such as key generation, lightweight authentication protocols, anti-counterfeiting and supply chain security. TRNG is another widely used hardware security primitive that makes use of noise and non-systematic variations of physical processes [1], [2] to support security-critical tasks such as secret or public key generations, seeds for cryptographic primitives and nonces

Results

Discussion

Conclusion