Abstract
In this paper, we present a semiclassical kinetic approach to tunnelling through potential barriers, which can be applied to the simulation of planar semiconductor devices. The proposed model includes thermionic emission currents at the metal–semiconductor interface as well as tunnelling currents together with the effect of barrier lowering. The considered scattering mechanisms are electron–phonon and electron–impurity interactions. The numerical scheme used is a combination of multicell methods with high-order shock-capturing algorithms. To demonstrate the applicability of the developed method, we present the characteristics of several silicon based Schottky barrier diodes.
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