Abstract

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

Highlights

  • With the proliferation of portable electronic products, the demand of high density nonvolatile memories [NVMs] has boosted tremendously

  • Flash memory based on charge trapping [CT] devices, such as silicon-oxide-nitride-oxide-silicon [SONOS] multilayer structure [3] and its various derivatives [4,5], has received renewed interest, and is extensively investigated recently

  • In this work, the Fowler-Nordheim [FN] tunneling mechanism was used for the program/erase [P/E] operations of the SONOS memory devices

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Summary

Introduction

With the proliferation of portable electronic products, the demand of high density nonvolatile memories [NVMs] has boosted tremendously. Flash memory based on charge trapping [CT] devices, such as silicon-oxide-nitride-oxide-silicon [SONOS] multilayer structure [3] and its various derivatives [4,5], has received renewed interest, and is extensively investigated recently. A thin-film transistor [TFT]-SONOS array is attractive for three-dimensional [3-D] multilayer stack structure for the purpose of ultrahigh memory cells density without aggressive scaling of device dimensions [8].

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