Abstract
A Josephson 4 bit register/arithmetic logic unit (RALU) which is adaptable to a prototype computer is discussed. The RALU circuit is designed to be composed of ALU, accumulator, registers for 10 bit instructions, 8 bit address, 4 bit data and carry flag, multiplexers, and so on. It consists of a four-junction logic (4JL) gate family of OR, AND, INVERT, and AMP gates. A complete set of photomasks of the RALU has been generated with the computer-aided-design system which performs an automatic standard cell layout, wiring, and logic check. The RALU chip has been fabricated using a 3 mu m Nb/AlO/sub x//Nb tunnel junction technology. Sixteen power voltage regulator junctions and 1273 logic gates are integrated on the 4.3*5 mm/sup 2/ chip. Operations have been confirmed for all 24 kinds of instructions in the RALU chip. Total power dissipation is 1.66 mW. A delay time of 300 ps has been evaluated for generating the SKIP signal to control the program address in the sequence control unit, which is essential to achieve one instruction execution for every high-speed clock cycle. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
