A Hybrid-Pipelined Architecture for FPGA-based Binary Weight DenseNet with High Performance-Efficiency

Abstract

The DenseNet achieves remarkable performance in various computer vision tasks with much fewer parameters and operations. However, there are few acceleration designs about the DenseNet, due to its dense-connectivity structure. In this paper, we apply the binary weight method on the DenseNet and then propose a hybrid-pipelined architecture for FPGA-based acceleration of the binary weight DenseNet, which can be stored entirely in a chip. To deal with the dense-connectivity, a reusable convolution unit is developed to support conv1×1 and conv3×3 efficiently. Moreover, a theoretical method of system parallelism is proposed to guide the top-level pipelined design for the maximum efficiency. To evaluate the proposed architecture, the binary weight DenseNet-100 model is trained on CIFAR10 dataset and then implemented on VX690T FPGA, at the cost of 4.18% accuracy loss. The experiment demonstrates that our architecture can achieve the throughput of 514 GOPS and 889 FPS at 200MHz, and the performance-efficiency is up to 62.4%, which outperforms the most related works.