A Hybrid Seven-Level Dual-Inverter Scheme With Reduced Switch Count and Increased Linear Modulation Range

Abstract

This work presents a hybrid seven-level dual inverter scheme with increased linear modulation range. The hybrid inverter structure is formed by supplying the load from primary side by using a cascaded structure of a two-level inverter and H-bridge (HB) and secondary side of the load is supplied by a floating-capacitor-fed two-level inverter. The combination of primary two-level space vector structure (SVS) with secondary two-level SVS and primary three-level SVS of HB form a seven-level SVS that can further be extended to an eight-level hexagonal SVS. This structure then reduced to a 12-sided eight-level SVS to avoid exceeding motor phase voltage rating. Subsequently by using this eight-level SVS in an unique pulsewidth modulation mode, the proposed topology can increase the modulation range linearly from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.577V_{\text{dc}}$</tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.637V_{\text{dc}}$</tex-math></inline-formula> peak phase fundamental voltage for any load power factor (pf), where dc-link voltage is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{dc}}$</tex-math></inline-formula> . An 11 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> increase in modulation range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.637V_{\text{dc}}/0.577V_{\text{dc}}$</tex-math></inline-formula> ) is possible devoid of lower order harmonics (predominantly <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$5{\text{th}}$</tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$7{\text{th}}$</tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$11{\text{th}}$</tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$13{\text{th}}$</tex-math></inline-formula> , etc.) in phase voltage for unity pf load in comparison to the conventional six-step operation of two-level and multilevel hexagonal SVS. To balance HB capacitors voltages in this work, a concept of indirect space vector redundancy is used. The efficacy of the proposed inverter scheme is verified through various experimental results at different steady-state and transient conditions.