A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

Abstract

In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide lower in-band noise than a bang-bang phase detector-based hybrid PLL (BB-HPLL). We also present noise analysis of the proposed PLL which shows that in-band noise can be further reduced by increasing the integral path gain, which is contrary to conventional design of BB-HPLLs where I path gain is minimized. A prototype chip fabricated in the 65-nm CMOS achieves 13-dB improvement of in-band phase noise compared to a conventional hybrid PLL and 2.08 psrms jitter at 4.8 GHz, while consuming 2.22 mW from a 1.0-V supply.