Abstract
A hybrid MPSoC (Multi-Processor SoC) simulator was proposed in this paper. The simulator provides statistical traffic model and behavior-level model for computation, along with cycle-accurate model on basis of ISS (Instruction-Set Simulator) including ARM and TI DSP. The simulator also provides NoC (Network-on-Chip) and traditional bus for on-chip communication and interconnection. As shown in the case study, the proposed simulator may improve the efficiency of building-up a multi-core simulation platform, and then may be used for simulation and evaluation of the constructed multi-core and NoC architectures.
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