Abstract
Recently, Multicore systems use Dynamic Voltage/Frequency Scaling (DV/FS) technology to allow the cores to operate with various voltage and/or frequencies than other cores to save power and enhance the performance. In this paper, an effective and reliable hybrid model to reduce the energy and makespan in multicore systems is proposed. The proposed hybrid model enhances and integrates the greedy approach with dynamic programming to achieve optimal Voltage/Frequency (Vmin/F) levels. Then, the allocation process is applied based on the available workloads. The hybrid model consists of three stages. The first stage gets the optimum safe voltage while the second stage sets the level of energy efficiency, and finally, the third is the allocation stage. Experimental results on various benchmarks show that the proposed model can generate optimal solutions to save energy while minimizing the makespan penalty. Comparisons with other competitive algorithms show that the proposed model provides on average 48% improvements in energy-saving and achieves an 18% reduction in computation time while ensuring a high degree of system reliability.
Highlights
IntroductionThe energy consumption of such multicore systems is increasingly rising
To process a massive amount of data, a possible solution is to use a large multicore system.The energy consumption of such multicore systems is increasingly rising
The safe voltage is slightly affected by the type of workload, on the other hand, it is affected by the operating frequency and number of cores
Summary
The energy consumption of such multicore systems is increasingly rising. This leads to an increase in cooling costs and reduces the reliability of the system components. In order to work efficiently, the power consumption and time limitations of multicore system chips become more important as the number of cores in a single chip is rising up. The power consumption is either static or dynamic. Dynamic Voltage/Frequency Scaling (DV/FS) is one of the major techniques used to manage a system’s power consumption. This technique can provide substantial power saving with a small performance loss if exists. The DV/FS strategy centered on detecting idleness in a device to scale down the frequency and optimize savings in energy to achieve minimal
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