A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers

Abstract

A hybrid Miller-Cascode compensation (HMCC) scheme incorporating Miller compensation (MC) and cascode compensation on a nonsignal path (CCNSP) in the two-stage amplifiers is presented. The proposed HMCC resolves issues in other compensations such as CCNSP, cascode compensation on a signal path (CCSP), and hybrid cascode compensation (HCC) such that the gain peaking near unity gain frequency (UGF) in the open-loop transfer function is alleviated, which results in faster settling. To understand and validate the merit of the proposed HMCC, the locations of poles and a zero are analyzed through the small-signal model and compared with other compensations in terms of settling speed. Moreover, to verify the effect of gain peaking on settling speed, two pipeline ADCs employing HMCC and CCNSP are fabricated in a 0.11- $\mu \text{m}$ CMOS process. In measurement, the ADCs with HMCC achieve higher spurious-free dynamic range (SFDR) at the sampling frequencies above 20 MHz than the ADCs with CCNSP, which demonstrates that the proposed HMCC achieves faster settling than CCNSP due to gain peaking suppression.