A Hybrid Fault Tolerant Approach for AES

Abstract

In this paper, a lightweight hybrid fault tolerant approach for AES, which is based on the integration of the algorithm based fault tolerant (ABFT) technique and the fault tolerant technique for s-box byte substitution operation is proposed. Two versions of scheme are presented to satisfy different application requirements. The first general version scheme can detect single error for the whole AES process with high efficiency. Another run-time version scheme is used to immediately terminate the error round with no time delay and no computation wasted on the rest rounds for propagating errors. Utilizing the ready-made arithmetic units in AES, single error can be detected by the sender and prevent the misdirected information from sending out. The results of the hardware FPGA implementation and simulation show that the proposed scheme can be integrated both on software and hardware without making many changes to the original AES implementation.