A Hybrid Compensation Scheme for the Gate Drive Delay in CLLC Converters

Abstract

The CLLC converter is often used as an isolated linker between high- and low-voltage buses where the CLLC converter operates under the open-loop condition at a resonant frequency. In such applications, CLLC converters are able to achieve high efficiency usually due to the superior performance of soft switching. However, we found that the operating process of a CLLC converter under open-loop control at the resonant frequency will significantly change by the nonideal parameters of the semiconductor switches and gate driver circuits. These impacts on the converter operation were investigated and defined as the gate drive delay. We present a comprehensive steady-state analysis for the CLLC converter that considers the gate drive delay including its operating process, mathematical model, power loss, and voltage ripple. In some cases, the gate drive delay changes the operating process of the CLLC converter. As a result, the soft-switching condition changes or even loses, large circulating current exists on the secondary side, output voltage ripples become larger, and so that the efficiency decreases dramatically. Therefore, a hybrid compensation scheme, consisting of an offline design procedure and an online closed-loop control algorithm, is proposed to minimize the resonant-frequency variation due to the gate drive delay. Both the correctness of the steady-state analysis and effectiveness of the proposed hybrid compensation scheme are verified by the experiment. Using the proposed compensation scheme can reduce the output voltage ripple to one-third of the original value and increase the efficiency by more than 10% within the whole load range.