A hybrid ASIC/FPGA fault-tolerant artificial pancreas

Abstract

This paper proposes a novel fault-tolerant human-implantable artificial pancreas integrated circuit achieving high dependability. The main objective of this work is to provide fault-tolerance to this safety-critical application and extend its lifetime similar to existing techniques such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR). The key idea is to explore a hybrid-substrate with an FPGA-like fabric attached to an Application-Specific Integrated Circuit (ASIC) that leverages DMR on a per-module basis to detect transient and permanent faults and ASIC and FPGA-like reconfiguration for correcting faults. When fault-tolerance against permanent faults is considered, the proposed architecture has 5,100x lower failure rate per hour than DMR with 2.4x area overheads. In the case where transient fault protection is required, our approach achieves 83x lower failure rate per hour than TMR with 1.6x area overheads.