A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Abstract

A biomedical stimulator with four high-voltage- tolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-µm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation. I. INTRODUCTION System-on-chips (SoC) for medical applications, such as retinal prosthesis (1) and epileptic seizure controller (2), had been proposed to implant into human body. The cochlear implant system is also one kind of medical applications for the profound deafness (3). Cochlear implant system is based on stimulating surviving auditory nerve in the inner ear to restore the hearing of deaf persons (4). The cochlear implant SoC for implanting into the human ear is illustrated in Fig. 1. The output from the stimulator is requested to provide adjustable high voltage to the electrodes those are implanted into the cochlea. The stimulator of the cochlear implant system may have a single channel or multiple channels, monopolar or bipolar stimulation, monophasic or biphasic pulse, and constant-current mode or constant-voltage mode (1), (5). The well-developed CMOS processes had been attractive to realize the implantable device for biomedical electronic applications. When the operation voltage of the stimulator is higher than the device normal operating voltage of a low-voltage CMOS process, the stimulator was usually implemented in the high- voltage CMOS process (6). From the biomedical application in our cochlear implant project, a stimulator with four-channel outputs in bipolar fashion, biphasic pulse, and constant-voltage mode is requested. According to the request of our biomedical project for cochlear implant, the required maximum voltage for stimulation is as high as 7 V. For SoC integration purpose, the other circuit blocks including data converter, DSP processor, and filters in the implant SoC device are all designed and realized in low-voltage CMOS process to reduce power consumption. So, the stimulator combined with high voltage generator implemented in low-voltage CMOS process is needed (7). Before any human test, the animal test to verify the function of SoC chip should be performed in advance. To design a power efficient output stage, the loading impedance of the specified biomedical application should be investigated first. So, the impedance of the cochlea of guinea pig was measured with the implanted electrodes, as that shown in Fig. 2(a). According to the measured impedance, the circuit model of the implanted electrodes with the cochlea has been calculated as that shown in Fig. 2(b). In this work, the stimulator with four-channel outputs is developed to drive the cochlea via the implanted electrodes, and it is implemented in a 0.18-µm 1.8-V/3.3-V CMOS process.