Abstract
In this paper, we propose a programmable tap structure used in a programmable FIR digital filter for high-frequency communication system, which speed performance is comparable to the case of a non-programmable filter. A fully parallel bit-level pipelined transposed-form carry-save architecture using CSD coefficients was used to achieve high-sample rate FIR digital filter. For realization of programmable filter coefficients, two decoders and some registers were added, and these registered data controlled the shifting process of input data using switch arrays.
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