A high-speed low-noise CMOS 16-channel charge-sensitive preamplifier ASIC for APD-based PET detectors

Abstract

A high-speed low-noise 16-channel amplifier integrated circuit (IC) has been fabricated in a 0.5 /spl mu/m CMOS process. It is a prototype for use with a PET detector that uses a 4/spl times/4 avalanche photodiode (APD) array having 3 pF of capacitance and 75 nA of leakage current per pixel. The preamplifier must have a fast rise time (a few ns) in order to generate an accurate timing signal, low noise in order to accurately measure the energy of the incident gamma radiation, and high density in order to read out 2-D arrays of small (2 mm) pixels. A single channel consists of a charge-sensitive preamplifier followed by a pad-driving buffer. The preamplifier is reset by an NMOS transistor in the triode region which is controlled by an externally supplied current. The IC has 16 different gain settings ranging from 2.1 mV/fC to 10.7 mV/fC. The gain is determined by four switched capacitors in the feedback loop. The switch state is set using a 64-bit shift register. A preamplifier 10%-90% rise time as low as 2.7 ns, with no external input load and 3.6 ns with a load of 5.8 pF was achieved. For the maximum gain setting and purely capacitive (5.8 pF) input load, the amplifier had 400 electrons root mean square (rms) noise at a peaking time of 0.7 /spl mu/s. When loaded with an APD pixel (/spl sim/3 pF capacitance, 125 nA leakage current), a noise minimum of 1550 electrons rms at a peaking time of 0.1 /spl mu/s is achieved. The IC is powered by a +3.3 V supply drawing 60 mA.