A high-speed, low latency RSA decryption silicon core

Abstract

This paper introduces a novel and generic approach to the hardware implementation of the RSA decryption function, which may be used to create digital signatures in an RSA based signature scheme. The algorithm used for modular multiplication is Montgomery's multiplication algorithm. The design is speed optimised and as such employs the R-L binary method as a means for modular exponentiation. An RSA decryption can be performed in only (k/2 + 3)/sup 2/ clock cycles, where k is the size of the modulus, by employing carry save adders in order to achieve fast parallel addition and the Chinese Remainder Theorem to speed up exponentiation. To the authors' knowledge, this is the lowest number of clock cycles required for any radix 2 based RSA decryption system reported in the literature. As such the design can achieve a data throughput rate of 234.47 kb/s for a 512-bit modulus and a rate of 90.58 kb/s for a 1024-bit modulus when implemented onto a Xilinx Virtex2 XC2V8000 chip.