A high-speed, hierarchical 16×16 array of array multiplier design

Abstract

Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. Some hybrid architectures called ‘array of array’ multipliers have intermediate performance. These multipliers have a time complexity better than array multipliers, and therefore becomes an obvious choice for higher performance multiplier designs of moderate operand sizes. In this paper a 16×16 unsigned ‘array of array’ multiplier circuit is designed with hierarchical structure and implemented using conventional CMOS logic in 0.6µm, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS. The proposed multiplier implementation shows large reduction in propagation delay and the average power consumption (at 20MHz) as compared to 16-bit Booth encoded Wallace tree multiplier by F Jalil [3]. The total transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of vias are also presented.