A high-resolution, high-linearity, two-step Time-to-Digital Converter for wideband counter-assisted ADPLL in 0.13um CMOS

Abstract

This paper presents a high-resolution, high-lineartity, two-step Time-to-Digital Converter(TDC) for wideband counter-assisted ADPLL. The proposed design uses two-step conversion scheme with buffer delay chain and Vernier delay chain, which realizes high resolution, wide range and period normalization in wideband ADPLL. The multiplexer between the two quantization stages is simple and inherently linear. This TDC is designed in 0.13um CMOS technology. Simulation results shows that 8ps resolution is achieved for 1.2G-2.5GHz ADPLL with reference frequency 40MHz.