A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch

Abstract

A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.