A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS

Abstract

An analog-to-digital converter (ADC) circuit is proposed that utilizes the linearity of the single-bit first-order sigma-delta in a first mode technique. In a second mode, successive approximation is used to convert the remaining voltage from the first conversion to increase the resolution without significantly increasing the conversion time. Both operations can be made in the same hardware, and only a counter is needed as decimation filter so that the converter becomes both area and power efficient. A channel of the ADC implemented in standard CMOS occupies an area of 40/spl times/1640 /spl mu/m/sup 2/. The control logic and reference voltage generation circuits, common for the ADC array, occupy a similar area. Estimated power consumption per ADC channel is about 0.5 mW including reference voltage generation. The conversion speed per ADC channel is 12.8 ksamples/s at a clock rate of 3.4 MHz. The ADC concept is suitable whenever a high resolution at a moderate speed is needed.