A high-resolution and fast-conversion time-to-digital converter

Chorng-Sii Hwang Chorng-Sii Hwang,Poki Chen Poki Chen,Hen-Wai Tsao Hen-Wai Tsao

doi:10.1109/iscas.2003.1205494

A high-resolution and fast-conversion time-to-digital converter

Chorng-Sii Hwang Chorng-Sii Hwang, Poki Chen Poki Chen + Show 1 more

https://doi.org/10.1109/iscas.2003.1205494

Copy DOI

Publication Date: May 25, 2003

Citations: 5

Affiliation: National Taiwan University of Science and Technology, National Taiwan University

#Time-to-digital Converter #Reference Clock Cycle + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The differential non-linearity (DNL) can be less than /spl plusmn/0.03 LSB and integral non-linearity (INL) less than /spl plusmn/0.04 LSB. We confirm the results based on 0.35 /spl mu/m CMOS process technology.

Full Text

Paper version not known

Open DOI Link

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Similar Papers

Paper Title

Journal

Date

Author

View more papers

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.