A High-Precision Wide Range On-Chip Path Delay Measurement

Abstract

On- chip delay measurement is one of the important procedures while the testing of the integrated circuits(IC) circuits is taken into consideration. Occurrence of the on chip delay is due to some defect in the IC at electrical level. Due to that defect there will be a delay in the movement of the signal to the destination. In order to improve the quality of shippable products, there is an urgent need to conduct effective delay testing for ascertaining the operation of chips at the rated frequency. In this paper, we present a on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. In the proposed on-chip path delay measurement(OCDM) circuit, several delay stages are employed, whose delay range is increased by a factor of two from the last to first delay stage. A calibration circuit is included to calibrate the delay range of the delay stage. Xilinx ISE based implementation was carried out. Simulation results shows precise measurement of path delays.