A High-Performance Distributed Amplifier Using Multiple Noise Suppression Techniques

Abstract

We demonstrate a 1.2-8.6 GHz two-stage distributed amplifier (DA) with cascade gain cell, which constitutes two enhanced CMOS inverters, using standard 0.18 μm CMOS technology. Multiple noise suppression techniques, including three noise-suppression/gain-peaking inductors and an RL terminal network, were used to achieve flat and low noise figure (NF) and flat and high power gain (|S21|) at the same time. At low-gain (LG) mode, the DA achieved |S21| of 11.41 ± 1.39 dB and an average NF of 3.74 dB for frequencies 1.2 ~ 8.6 GHz with a power dissipation (PDC) of 9.85 mW. At high-gain (HG) mode, the DA consumed 46.85 mW and achieved flat and high |S21| of 17.1 ± 1.5 dB with an average NF of 3.52 dB for frequencies 1.5 ~ 8.2 GHz.