Abstract
This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-added-efficiency (PAE) of 38% at its 1 dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4-5% at ≥4 dB back-off from its P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> . This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions.
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