A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

Abstract

This brief presents a highly synthesizable digital low-dropout regulator (DLDO) based on adaptive clocking and an incremental regulation scheme. With these features, the clock frequency of the shift registers is adaptively changed according to load voltage, and most of the voltage droop is stably recovered in one clock transition using voltage-unit-resolution pass gates. Moreover, the DLDO is fully synthesized using an auto place-and-route (P&R) process except pass gates and an on-chip metal-oxide-metal (MOM) output capacitor. Therefore, the synthesizable DLDO offers a scalable and portable architecture that has low design cost. The proposed DLDO is fabricated in the 28-nm CMOS technology with an active area of 0.0056 mm2. The ranges of input and output voltages are from 0.5 V to 1.0 V and from 0.45 V to 0.95 V, respectively. During recovery from a 2-mA load-current step with a 5-ns slew, the DLDO achieves 92-mV voltage droop and 83-ns settling time. The quiescent current is $7.87~\mu \text{A}$ , and the maximum load current and peak current efficiency are 4 mA and 99.8 %, respectively, with a 0.5-V supply.