A highly reliable and low-power cross-coupled 18T SRAM cell

Abstract

Static random access memory (SRAM) is a critical cell of VLSI, which is sensitive to the charge generated by high-energy particles and susceptible to logical errors. In this paper, the cross-coupled 18T SRAM cell (CC18T) is proposed, which uses the NMOS stack structure to reduce average power consumption, and employs redundant transistors to build a feedback loop to improve reliability. The model simulation results show that CC18T can fully achieve single-node-upset recovery and partial double-node-upset recovery. Compared with RHMD10T, QUCCE10T, QUCCE12T, We-Quatro, S4P8N, S8P4N, DNUCTM, DNUSRM, SESRS and SEA14T, the average power consumption of CC18T is reduced by 30% on average, the read access time and write access time are also reduced by 9.27% and 10.35% on average.