Abstract
The architecture of an experimental 8/16-bit peripheral processor is described. The chip was fabricated in a 2-μm NMOS technology with two metal layer. There are about 300 000 transistors on a chip area of 105 mm2. The average time for a read-modify-write instruction is 200 ns. A highly modular and regular design style and some automatically generated layouts resulted in a short design time.
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