A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder

Abstract

This paper presents a highly parallel hardware architecture for rate estimation in a High Efficiency Video Coding intra encoder to increase the level of parallelism and reduce the computational time. The adopted rate estimation algorithm is fully compatible with the context-adaptive binary arithmetic coding (CABAC) bit rate estimation except ignoring a syntax element “split_cu_flag.” Design considerations, analysis, and circuit implementation are elaborated. This design has been verified with the HM-15.0 reference software. It achieves an average decrease of 0.005% and an average increase of 0.0092 dB in Bjontegaard delta (BD)-rate and BD-peak signal-to-noise ratio, respectively. This proposed hardware architecture is implemented in Verilog and synthesized in FPGAs and ASICs. It supports resolutions up to $3840\times 2160$ at 30 f/s. Compared with state-of-the-art hardware designs for rate estimation in the literature, the proposed architecture achieves substantial performance improvement in rate estimation accuracy and reliability, with the overhead of a relatively larger chip area and higher power consumption. To the best of our knowledge, this is the first highly parallel hardware architecture of table-based CABAC bit rate estimator, which is attractive in time-constrained and high-performance video coding applications.