A High-linearity Phase Interpolator for 12.5Gbps Clock and Data Recovery Circuit of JESD204B Standard

Abstract

The JESD204B is a serializer interface between data converters and logic device. The paper presents a design of High-linearity phase interpolator for phase interpolator (PI)-based 12.5Gbps clock and data recovery (CDR) of JESD204B interface. This work puts forward a novel PI structure that only uses four reference phase that could generate eight phase clocks for the loop. In the aspect of ensuring the linearity of interpolation, this design develops one-step PI structure with a tangent function interpolation control method. Constant output amplitude and common voltage are guaranteed by the proposed structure and interpolation control method. In addition, to make the differential pairs of PI working in the saturation region, this work proposed a processing circuit that could adjust the reference clock. This PI occupies area of 0.03mm² and consumes a power of 21.6mW with a supply voltage 1.2V. The result shows that the average step and maximum of DNL and INL are respectively 0.53LSB and 0.35LSB, with 6.25GHz- reference clock. When the PI is added into CDR loop to provide eight phase 3.125GHz clocks, the loop performance is excellent.