Abstract
Video coding functions, such as discrete cosine transform (DCT), variable length coding and motion estimation, require a significant amount of processing power to implement in software. For high quality video or in applications where a powerful processor is not available, a hardware implementation is the solution. We propose a flexible field programmable gate array (FPGA) model, based on a high-level pipelined processor core, that can improve the performance of video coding. Furthermore, distributed arithmetic and exploitation of parallelism and bit-level pipelining are used to produce a DCT implementation on a single FPGA.
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