Abstract

Different from older generation of FPGAs, routing resources of recent FPGAs are described by hierarchical General Routing Matrix (GRM). In this paper, we present a routing algorithm which utilizes routing resources more efficient for GRM based FPGAs. First, we build routing resource graph (RRG) by a bottom-up way, then we combine breadth-first search manner with A* directed by a certain proportion to enhance utilization rate of routing resources, and this routing algorithm has high-adaptability to latest FPGA routing architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6% and 9% respectively.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.