A high throughput, ultra-low roughness, SiGe-free strained Si regrowth process

Abstract

We present simplifications to the strained Si wafer fabrication process that simultaneously improve wafer quality and process throughput. This process includes a short duration high-temperature bake and strained Si deposition directly on a planarized SiGe virtual substrate, without an intermediate low-temperature SiGe regrowth step between the planarized interface and the strained Si layer. By depositing the strained Si film directly on the planarized SiGe virtual substrate, we have developed a strained Si wafer manufacturing process featuring extremely low surface roughness (<0.2 nm RMS for 40×40 μm 2 scan atomic force microscopy scans, <0.1 nm RMS for 1×1 μm 2 scan atomic force microscopy scans), excellent interface abruptness, and the ability to achieve regrowth process cycle time better than 5 min/wafer.