A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders

Gabriele Meoni,Gianluca Giuffrida,Luca Fanucci

doi:10.3390/info10040151

Gabriele Meoni, Gianluca Giuffrida + Show 1 more

Open Access

https://doi.org/10.3390/info10040151

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Journal: Information	Publication Date: Apr 24, 2019
Citations: 1	License type: CC BY 4.0

Affiliation: University of Pisa

Abstract

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.

Highlights

During the last years, many applications, like space telecommunications systems [1], digital TV broadcasting [2] and wireless metropolitan area networks [3] have been exploiting forward error correcting (FEC) codes to reduce the bit error rate (BER) in data transmission
FECs encoders, like convolutional turbo codes (CTC) [6], which are realized by stacking recursive systematic convolutional (RSC) encoders in a parallel [7] or serial [8] configuration
Through an analysis of the implemented network topology, we present a methodology that permits us to estimate the dependency of the input data rate and of the field programmable gate array (FPGA) slice lookup tables (LUTs) on the parallelism degree

Summary

Introduction

Many applications, like space telecommunications systems [1], digital TV broadcasting [2] and wireless metropolitan area networks [3] have been exploiting forward error correcting (FEC) codes to reduce the bit error rate (BER) in data transmission. One of the most important FEC techniques is represented by recursive systematic convolutional (RSC) encoders. The latter are exploited as fundamental building block for the realization of more complex and efficient. FECs encoders, like convolutional turbo codes (CTC) [6], which are realized by stacking RSC encoders in a parallel [7] or serial [8] configuration. To supply the request of a higher transmission data rate [11] of modern telecommunication systems, research focused on increasing the efficiency of CTCs [1,12,13] or on improving their architecture at implementation level [12,14,15]

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