A High-speed Verilog HDL Simulation Method using a Lightweight Translator

Abstract

Designing with Hardware Description Languages (HDLs) is still the de facto standard way to develop FPGA-based custom computing systems, and RTL simulation is an important step in ensuring that the designed hardware behavior meets the design specification. In this paper, we propose a new high-speed Verilog HDL simulation method. It is based on two previously proposed techniques: ArchHDL and Pyverilog. ArchHDL is used as a simulation engine in the method because the RTL simulation provided by ArchHDL can be parallelized with OpenMP. We use Pyverilog to develop a code translator to convert Verilog HDL source code into ArchHDL code, and due to this, the translator can be realized and its implementation is lightweight. We compare the proposed method with Synopsys VCS, and the experimental results show that the RTL simulation behavior and speed are same as that of Synopsys VCS and up to 5.8x better respectively.