Abstract
An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.
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More From: IEEE Transactions on Circuits and Systems II: Express Briefs
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