Abstract
To achieve higher packing density for larger integration, various undesirable parasitic effects which degrade performance of each element must be primarily taken into account. This paper will describe a high speed 4096 bit bipolar shorted-junction type Schottky TTL PROM fabricated by the use of passive isolation techniques named “Shallow V Groove” (SVG) and “Isolation by Oxide and Polysilicon” (IOP). These two techniques have suppressed the undesirable parasitic effects and accomplished drastic improvement especially in both of cell size and speed by the factor of 1/2 and 2, respectively, as compared to those of our current gold doped device.
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