A high speed low power pulse swallow frequency divider for DRM/DAB frequency synthesizer

Abstract

The implementation of a high-speed low-power pulse swallow frequency divider for a DRM/DAB frequency synthesizer, using a 0.18-μm CMOS technology, is described. The frequency divider employs a divide-by-32/33 dual-modulus prescaler, a five bits swallow counter, an 11 bits programmable counter, and a control circuit necessary for the time sequence and operation of the division. In the pulse swallow frequency divider, the divide-by-32/33 dual-modulus prescaler consists of a divider-by-4/5 and an asynchronous divider-by-8 frequency divider, the swallow counter and the programmable counter consist of static-logic fall edge-triggered DFFs. The structure is designed to reduce the power consumption. Post-simulated results show that the programmable divider's operation frequency is from 0.5 GHz to 3.5 GHz with a maximum power consumption of 3.01 mW at 1.8V power supply. The dimension of pulse swallow frequency divider is 270 μm×110 μm.