A high speed graphics DRAM with low power and low noise data bus inversion in 54nm CMOS

Abstract

This paper presents a high speed 1Gb GDDR3 Graphics DRAM using data bus inversion (DBI) DC mode in order to achieve low power and low noise in DRAM. A DBI, digital majority voter (DMV) circuit and the Global I/O (GIO) control circuit on the DBI DC mode are newly proposed. In this DMV, The current of GIO toggle pattern is consumed less than 47% compared with the analog majority voter (AMV). The voltage fluctuation wave form of the data eye is also reduced in accordance with DBI on the operation mode. Using the proposed DBI scheme can produce almost stable signal integrity of the DQs against high speed operation. The DBI is fabricated using 54nm technology.