A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs

Abstract

In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed. It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC). The multiplier is realized by a radix-4 Booth encoding based on sign-magnitude inputs. The FAAC contains a bidirectional shift alignment, a fast 3:1 compressor, and a three-operand leading-zero predictor (LZP). Due to the simplification of implementation steps, a short critical path, and a full-pipelined structure, our FPMAC achieves a high running speed while sustaining the good performance of delay and resource consumption. We have implemented and evaluated our FPMAC on two devices from Xilinx. Compared with two contrast FPMAC architectures, the results show that the maximum clock frequencies of our FPMAC increase by 33.4%–74.4% in single-precision floating-point (SFP) and 15.8%–86.1% in double-precision floating-point (DFP).