Abstract
This paper describes a high-speed arithmetic unit which utilizes a ``sub-multiple algorithm'' in both multiplication and division. The organization and circuits, which make the algorithm practical and economical, are presented. High performance in the unit is achieved by the use of tunnel diodes in four key areas, namely, in a tunnel diode memory using nondestructive readout, in the memory selection drivers, in a tunnel diode adder and in a bidirectional shift register. The unit performs a fixed point binary multiplication and division of two 44-bit operands in 2.75 μsec and 12 μsec, respectively. An experimental arithmetic unit has been built and operated in conjunction with a computer. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> Propagation delays of less than 2.2 nanoseconds were achieved between logic stages of a 48-bit binary full adder. Some results of the evaluation tests are also discussed.
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