A High Speed and Power Controlled CMOS Edge Detector for 2.5 Gb/s Clock Recovery Circuit

Abstract

The ever-growing demand to high-speed transmission of data has forced the designers to make faster and much more reliable circuits and systems for users. Among many of methodologies for data formats to be transmitted, the binary data is of great interest. There are various pulse code modulations (PCM) for transmission of binary data among which, non return to zero (NRZ) and return to zero (RZ) are well-known. RZ is more reliable and easier to use in comparison with NRZ but it is slower. Since there is no zero between any two bits in NRZ, its bit rate is two times more than that of RZ in the same conditions. But this reality makes the designers to consider an edge detector for NRZ data. This paper introduces a novel edge detector designed for 2.5 Gb/s clock recovery circuit. This baud rate represents the free-running frequency of phase locked loop (PLL). The advantage of this edge detector is its flexibility to encounter with frequency changes. Moreover, it doesn't dissipate constant power meaning that its dissipated power is proportional to the frequency of the received data. Therefore the jitter and extra power dissipation produced by conventional edge detectors are removed. Finally, the simulation of this edge detector for a 0.18 mum technology and its comparative results are given.