A High-Speed and Low-Power Inverter Circuit Using p-Channel Metal Oxide Semiconductor Low-Temperature Polycrystalline Silicon Thin Film Transistors

Abstract

Whereas p-channel metal oxide semiconductor (PMOS) thin film transistor (TFT) circuits can reduce the fabrication cost because of the smaller number of masks and simpler process steps compared with the complementary metal oxide semiconductor (CMOS) counterparts, the circuit performance is very limited and power consumption is an issue. A previously reported PMOS TFT inverter circuit can alleviate the issues encountered in the conventional PMOS TFT circuits such as high power consumption and limited output dynamic range. However, the circuit uses an auxiliary negative supply voltage for full output dynamic range, requiring an additional DC–DC converter. We newly propose a PMOS TFT inverter circuit that eliminates an auxiliary negative supply voltage and provides high-speed operation and low power consumption. The circuit intentionally creates a delay of the input signal to generate a negative voltage for turning on the pull-down PMOS TFTs and allowing the output to drop to ground level. The rising and falling times are reduced to 35.5 and 15.6% of those of the previous PMOS TFT inverter, and the power consumption is also reduced to 55.6%.