A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

Abstract

A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.