Abstract
In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.
Highlights
A digital-to-time converter (DTC) is used to generate a time signal with a width that is proportional to the programmable input digital value
In terms of implementing methods, the DTCs can be classified as application specific integrated circuit (ASIC) DTC [1,2,3,4,5,6,7,9] and field programmable gate arrays FPGA-DTC [6,8,11]
Sci.or2019, Since the logic gates in programmable delay line (PDL) are synchronized to SF and the logic gates in pulse generators are synchronized to SM or SS, the latency mismatch between these signals would cause time error on DTC
Summary
A digital-to-time converter (DTC) is used to generate a time signal with a width that is proportional to the programmable input digital value. The absolute time generations have wide dynamic ranges but poor resolution performance They are sensitive to process, voltage and temperature (PVT) variations. A DTC based on the Vernier principle was proposed in [11] It achieved a 1.58 ps resolution using two integrated PLLs with Altera Stratix-III FPGA. Vernier DTC and QPSR DTC realized with Xilinx Virtex-5 FPGA only obtained 35.27 ps and 27.1 ps resolution, respectively. Vernier DTCs and QPSR DTCs implemented with the same FPGAs. the DTC obtains 13.5 ps resolution even with the cheapest Altera Cyclone-IV E FPGAs. The high-resolution performance of the proposed DTC benefits from the high, medium and slow Vernier delay line constructed by PLLs, which ensures fine resolution and robustness to PVT variation.
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